1. Field of the Invention
The present invention relates to an input circuit in a semiconductor integrated circuit and, more particularly, to an input circuit comprising complementary MOS transistors.
2. Description of the Related Art
FIG. 1 shows a conventional inverter used as an input circuit in a CMOS semiconductor integrated circuit. This inverter has the following configuration. A p-channel MOSFET 71 is connected between the node of a power source voltage Vcc and an output node Out. An n-channel MOSFET 72 is connected between the output node Out and the node of a ground voltage Vss. The gates of the MOSFETs 71 and 72 are connected to an input node In.
FIG. 2 shows a conventional two-input NAND circuit used as an input circuit in a CMOS semiconductor integrated circuit. This NAND circuit has the following configuration. A p-channel FET 73 is connected between the node of a power source voltage Vcc and an output node Out. Two n-channel MOSFETs 74 and 75 are connected in series between the output node Out and the node of a ground voltage Vss. A p-channel MOSFET 76 is connected between the node of the power source voltage Vcc and the output node Out. Two n-channel MOSFETs 77 and 78 are connected in series between the output node Out and the node of the ground voltage Vss. The gates of the MOSFETs 73, 74, and 78 are commonly connected to a first input node In1. The gates of the FETs 75, 76, and 77 are commonly connected to a second input node In2.
FIG. 3 shows a conventional two-input NOR circuit used as an input circuit in a CMOS semiconductor integrated circuit. This NOR circuit has the following configuration. Two p-channel MOSFETs 79 and 80 are connected in series between the node of a power source voltage Vcc and an output node Out. An n-channel MOSFET 81 is connected between the output node Out and a ground voltage Vss. Two p-channel MOSFETs 82 and 83 are connected in series between the node of the power source voltage Vcc and the output node Out. An n-channel MOSFET 84 is connected between the output node Out and the node of the ground voltage Vss. The gates of the FETs 79 and 83 are commonly connected to a second input node In2. The gates of the FETs 80, 81, 82, and 84 are commonly connected to a first input node Inl.
In an input circuit such as an inverter, a NAND circuit, and a NOR circuit comprising MOSFETs, it is known that when the threshold voltages of the MOSFETs vary, the circuit threshold voltage also varies. When a TTL-level signal is input as an input signal, the rated range of the input noise margin becomes wider than in a case when a CMOS-level signal is input as an input signal. Therefore, it is necessary to take a measurement to minimize a variation in the circuit threshold voltage.
The circuit threshold voltage of each of the conventional input circuits described above varies largely when the threshold voltages of two types of FETs, i.e., p- and n-channel MOSFETs, vary complementarily to each other. For example, FIG. 4 shows an equivalent circuit of the inverter shown in FIG. 1 of a case wherein the potential of the input node In reaches a value close to the circuit threshold voltage. In this case, assuming that the ON resistances of both p- and n-channel MOSFETs are R and are thus the same, the output potential becomes half the power source voltage Vcc.
Generally, a circuit threshold voltage VthC of an inverter as shown in FIG. 1 is expressed by the following equation (1): ##EQU1## where Vcc: power source potential;
.beta..sub.P : .beta. value of p-channel MOSFET; PA1 .beta..sub.N : .beta. value of n-channel MOSFET; PA1 .vertline.Vthp.vertline.: threshold value (absolute value) of p-channel MOSFET; and PA1 VthN: threshold value of n-channel MOSFET
When equation (1) is simplified by substituting a condition .beta..sub.P =.beta..sub.N, the following equation (2) is obtained: ##EQU2##
From equations (1) and (2), it can be understood that the circuit threshold voltage varies when the threshold voltages of two types of MOSFETs constituting an inverter fluctuate complementarily to each other, i.e., such that .vertline.Vthp.vertline. becomes larger than VthN or alternatively, .vertline.Vthp.vertline. becomes smaller than VthN. In other words, when an input potential reaches a level close to the circuit threshold voltage of the inverter, the ON resistance fluctuates, resulting in a variation in circuit threshold voltage.
FIG. 5 shows an equivalent circuit of the inverter of FIG. 1 of a case wherein the ON resistance of the p-channel MOSFET is changed from R to R + .DELTA.R and that of the n-channel MOSFET is changed from R to R -.DELTA.R. The output potential Vout of the equivalent circuit of FIG. 5 is defined by the following equation (3): ##EQU3##
FIG. 6 shows the equivalent circuit of a case wherein the ON resistance of the p-channel MOSFET is changed from R to R - .DELTA.R and that of the n-channel MOSFET is changed from R to R +.DELTA.R, contrary to the above case. The output potential Vout of this equivalent circuit is defined by the following equation (4): ##EQU4##
In this manner, in the conventional inverter, when the threshold voltage of an FET varies, the circuit threshold voltage varies, posing a problem.
The same problem as this also arises in the NAND circuit of FIG. 2 or the NOR circuit of FIG. 3 in which p-channel and n-channel MOSFETs are connected in series between the node of the power source voltage Vcc and the node of the ground voltage Vss.
When an input signal is anticipated to be influenced by a disturbance, a Schmitt trigger circuit is usually used as an input circuit. FIG. 7 shows the configuration of a conventional Schmitt trigger circuit. This circuit has the following configuration. Two p-channel MOSFETs 91 and 92 are connected in series between the node of a power source voltage Vcc and a node N11. Two n-channel MOSFETs 93 and 94 are connected in series between the node N11 and the node of a ground voltage Vss. A signal from an input node In is supplied to the gates of the FETs 91, 92, 93, and 94. A signal appearing at the node N11 is sequentially inverted by two series-connected inverters 95 and 96 and is derived as an output signal. A p-channel MOSFET 97 is connected between a node N12 of the series-connected FETs 91 and 92 and the node of a ground voltage Vss. An n-channel MOSFET 98 is connected between a node N13 of the series-connected FETs 93 and 94 and the node of the power source voltage Vcc. An output signal from the inverter 96, i.e., a signal at an output node Out is supplied to the gates of the FETs 97 and 98.
The operation principle of this Schmitt trigger circuit will be briefly described. When the signal at the input node In is at the ground voltage Vss (to be referred to as "L" hereinafter), a potential Vb at the node N13 is set at Vcc - VthN by the FET 98. As the potential of the input signal is increased, the potential Vb is decreased. An input potential at which the FET 93 starts to be turned on is Vb' + VthN (where Vb' is a potential defined depending on the element constant of the FETs 94 and 98 and an input potential). If the FET 98 as the feedback element is not provided, the input potential at which the FET 93 starts to be turned on is VthN. When the FET 98 is added, the circuit threshold voltage upon a change in input from "L" to the level of the power source voltage Vcc (to be referred to as "H" hereinafter) is increased by Vb'.
When the input signal is "H", a potential Va at the node is set at .vertline.Vthp.vertline. by the FET 97. As the potential of the input signal is decreased, the potential Va is increased. The input potential at which the FET 92 starts to be turned on is Va'+ .vertline.Vthp.vertline. (where Va' is a potential defined depending on the element constant of the FETs 91 and 97 and an input potential). When the FET 97 as a feedback element is not provided, the input potential at which the FET 92 starts to be turned on is Vcc - .vertline.Vthp.vertline.. When the FET 97 is added, the circuit threshold voltage upon a change in input from "H"to "L" is decreased by Vcc - Va'. Then, a potential difference between Vb' + VthN and Vcc - .vertline.Vthp.vertline. becomes the hysteresis voltage width.
In the conventional Schmitt trigger circuit, assume that the Schmitt characteristics are to be realized within a predetermined input margin, i.e., within a range that e.g., when the power source voltage Vcc is 2V, the minimum high-level input potential (VIHmin) is 1.5V, and the maximum low-level input potential (VILmax) is 0.5V; when the power source voltage Vcc is 5V, VIHmin is 3.5V and VILmax is 1.5V, while setting a hysteresis voltage width as wide as possible. Then, the actual characteristics are largely restricted by the influence of the variation in the threshold voltages of the FET, especially under a low power source voltage. In other words, when the power source voltage is 5V, a sufficient input noise margin is assured. Nevertheless, if the hysteresis voltage width is set larger than the rated margin, the Schmitt characteristics undesirably fall outside the rated margin when Vcc is 2V.
As described above, in the conventional inverter, NAND circuit, NOR circuit, or Schmitt trigger circuit used as the input circuit in the conventional CMOS semiconductor integrated circuit, when the threshold voltage of a transistor varies, the circuit threshold voltage also greatly varies. In particular, in a Schmitt trigger circuit, due to the influence of the variation in the circuit threshold voltage, the hysteresis voltage width at a low power source voltage cannot be increased.